The present invention relates to a method of manufacturing a circuit device, particularly to a method of manufacturing a circuit device of thin type not needing a supporting substrate.
Up to now, since a circuit device set to an electronic instrument is used for a portable telephone, a portable computer, and the like, miniaturization, thin type, and light weight are required.
For example, describing an example of semiconductor device as a circuit device, there is a package type semiconductor device sealed with a usual transfer molding as a general semiconductor device up to now. The semiconductor device is molded on a printed circuit board PS as shown in FIG. 18.
In the package type semiconductor device, periphery of a semiconductor chip 2 is covered with a resin layer 3, and a lead terminal 4 for an external connection is led out from a side portion of the resin layer 3.
However, in the package type semiconductor device 1, the lead terminal 4 comes out from the resin layer 4, and size of the whole is too large to satisfy the request for miniaturization, thin type, and light weight.
Because of that, each company develops various kind of structure with competition to realize miniaturization, thin type, and light weight, and nowadays a wafer scale CSP similar in size as size of a chip, or a CSP some larger in size than the chip size, they are called CSP (chip size package), is developed.
FIG. 19 shows a CSP 6 adopting a glass epoxy substrate 5 as the supporting substrate and some larger than the chip size. Here, it is described as that a transistor chip T is molded on the glass epoxy substrate 5.
A first electrode 7, a second electrode 8, and die pad 9 are formed at the front face of the glass epoxy 5, and the rear face, a first rear face electrode 10 and a second rear face electrode 11 are formed. The first electrode 7 and the first rear face electrode 10, and the second electrode 8 and the second rear face electrode 11 are connected electrically through through-holes TH. The bare transistor chip T is fixed at the die pad 9, the emitter electrode of the transistor chip T and the first electrode 7 are connected through a metal fine wire 12, and the base electrode of the transistor chip T and the second electrode 8 are connected through a metal fine wire 12. Further, the resin layer 13 is provided on the glass epoxy substrate 5 so as to cover the transistor chip T.
The CSP 6 has merits that extending structure from the chip T to the rear face electrodes 10 and 11 for external connection is simple and it is produced in low cost differing from the wafer scale CSP though the glass epoxy substrate 5 is adopted.
Further, the CSP 6 is mounted on the printed circuit board PS as shown in FIG. 18. On the printed circuit board PS, electrodes and wiring forming an electric circuit are provided, and the CSP 6, the package type semiconductor device 1, chip resistors CR, or chip capacitors CC are connected electrically and fixed.
The circuit constructed by the printed circuit board is attached in various kinds of sets.
Next, a method of manufacturing the CSP will be described referring FIGS. 20A to 20D and FIG. 21.
First, the glass epoxy substrate 5 is provided for a base material (supporting substrate), Cu foils 20 and 21 are pressure bonded to both faces of the substrate through insulating adhesive. (See FIG. 20A)
Next, resist 22 having etching resistance property is covered on the Cu foils 20 and 21 corresponding to the first electrode 7, the second electrode 8, die pad 9, the first rear face electrode 10, and the second rear face electrode 11, and patterning the Cu foils 20 and 21 are performed. The patterning may be performed separately at front and rear faces. (See FIG. 20B)
Next, holes for the through-holes TH are formed at the epoxy substrate using drill and laser, and the through-holes TH are formed by plating the holes. By the through-holes, the first electrode 7 and the first rear face electrode 10, and the second electrode 8 and the second rear face electrode 10 are connected electrically. (See FIG. 20C)
Further, although not shown in the figures, Au plating is performed to the first electrode 7 and the second electrode 8 to be bonding posts, Au plating is performed to the die-pad becoming die-bonding post, and the transistor chip is die-bonded.
Finally, the emitter electrode of the transistor chip T and the first electrode 7, and the base electrode of the transistor chip T and the second electrode 8 are connected through the metal fine wires 12, and covered with the resin layer 13. (See FIG. 20D)
By the above method of manufacturing, electric elements of CSP type adopting the supporting substrate 5 are completed. The method of manufacturing is similar as by adopting a flexible sheet as a supporting substrate.
Although the transistor chip T, the connecting member (the first electrode 7, the second electrode 8, the die pad 9, the first rear face electrode 10, the second rear face electrode 11, and metal fine wire 12) and the resin layer 13 are required component elements on connecting to the outside and protecting the transistor in FIG. 18, it is difficult to provide circuit elements realizing miniaturization, thin shape, and light weight with such the component elements.
The glass epoxy substrate 5 being the supporting substrate is needless originally as described above. However, on the method of manufacturing, the substrate is adopted as a supporting substrate to bond the electrodes, so it is not possible to remove the glass epoxy substrate 5.
Because of that, by adopting the glass epoxy substrate 5, cost rises, further because the glass epoxy substrate 5 is thick, the circuit elements become thick so that there is a limit for miniaturization, thin shape, and light weight.
Further, through-hole forming process connecting electrode of both faces is always indispensable at the glass epoxy substrate and ceramic substrate, and there is a problem not fitting to mass production because manufacturing process becomes long.
In the view of the above problems, the applicant developed a circuit device making the supporting substrate needless in Japanese Patent Publication No. 2002-76238. However, position recognition of conductive pattern is performed at every mounting portion to form an opening for soldering electrode in the process covering the rear face resist so that there is a problem that it takes long time to recognize the position.